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Simulating Quantum Computers: Innovation in Verification

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Simulating Quantum Computers: Innovation in Verification By Bernard Murphy | December 29, 2025 | 6:00 AM Categories: Cadence, EDA, Quantum Computing Introduction Quantum computing is transitioning from theoretical research to practical engineering reality. As investment and innovation accelerate, a fundamental challenge emerges: how do we verify quantum algorithms and circuits before reliable, large-scale quantum hardware is widely available? The answer lies in quantum simulation on classical computers . While verification through simulation is familiar in classical digital design, quantum simulation introduces fundamentally different mathematical models, computational scaling challenges, and verification philosophies. This blog explores recent research that sheds light on how quantum circuits can be simulated, understood, and validated using classical computing infrastructure. Why Quantum Simulation Matters Quantum algorithms must be validated long before they can be deploye...
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Assertion-First Hardware Design and Formal Verification Services

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  Assertion-First Hardware Design and Formal Verification Services  | Categories: AI, EDA, LUBIS EDA Introduction: Why Verification Still Dominates Hardware Schedules Generative AI has dramatically accelerated software development, and similar advances are now appearing in RTL generation for hardware. Entire RTL blocks can be produced quickly, often from high-level descriptions or prompts. However, while RTL creation is becoming faster, verification remains the dominant bottleneck in hardware development. Proving that hardware behaves correctly under all possible conditions is fundamentally more difficult than generating syntactically correct logic. This challenge has renewed interest in a long-standing idea in hardware engineering: assertion-first design —a methodology where design intent is formally specified before RTL is written. For decades, this approach was widely acknowledged as ideal but practically unattainable. Today, that reality is changing. AI Can Generate ...
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3D ESD Verification: Tackling New Challenges in Advanced IC Design

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  3D ESD Verification: Tackling New Challenges in Advanced IC Design Categories: 3D IC, EDA, Siemens EDA Introduction As semiconductor designs evolve toward heterogeneous 2.5D and 3D integration, long-established verification methodologies are being pushed beyond their limits. One area where this shift is especially evident is electrostatic discharge (ESD) verification. While ESD protection has been well understood in traditional 2D ICs, stacked-die architectures introduce new connectivity, new failure modes, and new verification complexity. Addressing these challenges requires a fundamentally different approach. This blog explores why ESD verification is critical for 3D ICs, what makes it more complex than conventional designs, and how modern automation tools enable reliable and cost-effective verification. Why ESD Verification Is Critical for 3D IC Designs Electrostatic discharge remains one of the most common causes of IC damage throughout the product lifecycle—from wafe...
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Superhuman AI for Design Verification, Delivered at Scale

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  Superhuman AI for Design Verification, Delivered at Scale Introduction The semiconductor industry is entering a new era—one where traditional EDA tools can no longer keep pace with the scale of data, complexity of multi-chip systems, and the verification demands of modern AI-driven architectures. As verification datasets explode and debug tasks grow more intricate, engineering teams face an unsustainable workload. In this landscape, Bronco AI introduces a superhuman, scalable AI platform designed specifically for design verification —one that integrates seamlessly into existing flows, accelerates debug, and continuously improves while protecting customer IP. This is not incremental progress. It is a paradigm shift. The Verification Challenge For decades, EDA innovation has centered on producing better chips—higher performance, lower power, faster time to market. Verification and debug have always been essential steps in this process. But the world has changed: AI model...
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Hierarchically Defining Bump and Pin Regions Overcomes 3D IC Complexity

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  Hierarchically Defining Bump and Pin Regions Overcomes 3D IC Complexity Categories: 3D IC, Chiplet, EDA, Siemens EDA Key Takeaways Chiplets offer modular, flexible, and cost-efficient system integration but also significantly increase package assembly complexity. Hierarchical device planning is essential for abstracting and managing the rising intricacies of modern IC packaging. Early SI/PI and thermal analysis is critical to avoid costly redesigns and guide key architectural decisions throughout the design cycle. By Todd Burkholder and Per Viklund, Siemens EDA Introduction: The Rise of Chiplets and the Complexity Challenge Advanced IC packaging is undergoing a transformation. As the semiconductor industry shifts toward heterogeneous integration , designers are merging diverse chiplets, dies, interposers, and bridges into unified 3D-stacked systems. This approach delivers unprecedented flexibility and performance — but dramatically increases design complexity. ...
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Boosting SoC Design Productivity with IP-XACT

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  Boosting SoC Design Productivity with IP-XACT Categories: Accellera, Semiconductor Services Modern System-on-Chip (SoC) designs are composed of hundreds of IP blocks—CPUs, accelerators, NoCs, peripherals, and mixed-signal components—all of which must seamlessly integrate. As complexity accelerates, so does the potential for miscommunication, integration errors, and manual bottlenecks. IP-XACT (IEEE 1685) has emerged as one of the most effective solutions to unify, automate, and scale SoC design. This blog explores what IP-XACT is, why it matters, and how the latest enhancements enable productivity gains across semiconductor teams. What Is IP-XACT? IP-XACT is a standardized, machine-readable XML schema that describes semiconductor intellectual property (IP) blocks and system-level assemblies. The format captures: Interfaces, ports, and bus definitions Memory maps and register specifications Structural hierarchy and parameters Configuration metadata and design vi...
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FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges Categories: EDA, Emulation, Prototyping. Key Takeaways Modern chip verification struggles with peripheral connectivity due to major differences in operating frequencies. Speed adaptors bridge systems running at different speeds, enabling real-world transaction-level verification. PCIe, HDMI, and memory models are three major use-cases where speed adaptors solve prototyping challenges. S2C provides a comprehensive range of speed adaptors, memory models, and daughter cards for high-speed interface support. With 20+ years of expertise, S2C continues to advance FPGA prototyping technology, reducing verification cycles and accelerating time-to-market. Introduction Modern chip design verification is becoming increasingly complex. One of the biggest challenges is connecting real-world peripherals to FPGA prototypes or emulation platforms. User designs often run at tens of megahertz—or in some cases e...
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