Siemens EDA Accelerates Custom IC Design with Additive Learning

 

Siemens EDA Accelerates Custom IC Design with Additive Learning

Custom IC design teams are under constant pressure to achieve SPICE-accurate, variation-aware verification—while reducing turnaround time across iterative design cycles. Traditional Monte Carlo approaches are too slow, and approximation techniques often miss outliers or non-Gaussian behavior.

A recent webinar highlighted how additive learning is transforming this workflow within the Solido Custom IC Platform.

The Challenge in Custom IC Verification

Modern analog and mixed-signal designs require:

  • Full PVT corner coverage

  • Monte Carlo variation analysis

  • High-sigma yield verification

  • Frequent re-verification due to:

    • PDK updates

    • Transistor sizing changes

    • Added corners

    • Simulator revisions

Each iteration traditionally requires re-running expensive simulation campaigns, extending project timelines significantly.



The Additive Learning Approach

Within the Solido Design Environment:

  • PVTMC Verifier delivers 2×–10× speed-up while maintaining SPICE accuracy

  • High-Sigma Verifier enables 6-sigma yield verification with up to 1,000×–1B× speed-up versus brute force

  • The Additive Learning Engine retains and reuses AI models from prior runs

Instead of restarting verification from scratch, the system incrementally builds knowledge across iterations, achieving:

  • 3×–20× faster incremental runs

  • Fewer simulations

  • Automated AI model reuse

  • No additional AI expertise required from users

The AI datastore is lightweight, optimized, and supports multi-user environments with minimal storage overhead.



Real-World Results from Microchip

In practical deployments:

Bandgap Reference Circuit (Pre-layout, 3σ, 21 PVT corners):

  • Base: 885 simulations | 2h 16m

  • AL Off: 1,170 simulations | 3h 24m

  • AL On: 315 simulations (3.7× fewer) | 49m (4.1× faster)

RC Oscillator (Post-layout, 3σ, 1 PVT corner):

  • Base: 300 simulations | 14h 16m

  • AL On: 15 simulations (20× fewer) | 39m (18× faster)

These results were showcased at DAC 2025, demonstrating measurable gains in real silicon design workflows.



Why This Matters

Additive learning fundamentally changes iterative verification economics:

  • Eliminates redundant simulation effort

  • Preserves SPICE accuracy

  • Dramatically shortens design cycles

  • Requires no AI tuning or user intervention

For custom IC teams navigating tight schedules and complex variation analysis, additive learning offers a scalable, production-ready solution to accelerate verification without compromising quality.



AI in EDA is no longer experimental—it is delivering quantifiable productivity gains where they matter most: iteration speed and verification accuracy.

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