Assertion-First Hardware Design and Formal Verification Services

 

Assertion-First Hardware Design and Formal Verification Services

 | Categories: AI, EDA, LUBIS EDA

Introduction: Why Verification Still Dominates Hardware Schedules

Generative AI has dramatically accelerated software development, and similar advances are now appearing in RTL generation for hardware. Entire RTL blocks can be produced quickly, often from high-level descriptions or prompts. However, while RTL creation is becoming faster, verification remains the dominant bottleneck in hardware development. Proving that hardware behaves correctly under all possible conditions is fundamentally more difficult than generating syntactically correct logic.

This challenge has renewed interest in a long-standing idea in hardware engineering: assertion-first design—a methodology where design intent is formally specified before RTL is written. For decades, this approach was widely acknowledged as ideal but practically unattainable. Today, that reality is changing.

AI Can Generate RTL, but Verification Is Still the Hard Part

AI-generated RTL can appear correct and well-structured, yet hardware correctness has no tolerance for ambiguity. Unlike software, hardware errors cannot be patched after deployment. Moreover, AI models trained on similar datasets often share similar blind spots, meaning that using AI to verify AI-generated RTL may amplify rather than eliminate risk.

Verification continues to consume the majority of engineering time and budget because it requires precise, unambiguous intent. Without a mathematically defined specification, completeness and correctness cannot be guaranteed. This is where Assertion IP becomes critical.

Assertion IP: The Missing Foundation of Hardware Design

Assertion IP captures design intent in its most rigorous form. Assertions formally define how a design must behave across clock cycles, states, inputs, and transitions. In an ideal workflow, assertions act as the executable specification, and RTL is simply one implementation that must satisfy those properties.

Had hardware design started with assertions from the beginning, ambiguity would be reduced, verification would be more systematic, and formal proof could be applied throughout the development lifecycle—not just at the end.

Why Assertion-First Design Was Historically Out of Reach

Despite its appeal, assertion-first design was impractical for most real-world projects:

• Writing hundreds or thousands of assertions manually was slow and error-prone

• High-level modeling languages lacked consistency and analyzability

• Automated property generation tools did not exist

• Formal verification engines could not handle large designs or deep state spaces

As a result, the industry adopted an RTL-first culture, where assertions were added late in the flow, often as incomplete checkers rather than a complete behavioral specification.

What Has Changed: Technology Has Finally Caught Up

Recent advances have fundamentally altered the feasibility of assertion-first hardware design:

• High-level model analysis engines can extract states, transitions, invariants, and dataflow from C++ and SystemC models

• Automated property generation can produce comprehensive assertion suites directly from executable models

• Modern formal engines can scale to complex pipelines, cryptographic logic, and large state spaces

• AI assistance simplifies the creation of structured, analyzable models from high-level intent

Together, these developments make it possible to define correctness before RTL is written—and to prove it formally.

Where LUBIS EDA Fits In

LUBIS EDA is turning assertion-first design from theory into practice. Its technology automatically generates complete Assertion IP from high-level executable models, creating a direct bridge between abstract intent and RTL implementation.

Through refinement techniques, LUBIS aligns abstract models with cycle-accurate, bit-true RTL, ensuring that generated properties reflect real hardware behavior. Combined with LUBIS EDA’s formal verification services and targeted training, teams can adopt assertion-driven workflows and achieve formal sign-off on complex IP blocks.

As AI accelerates RTL generation, this model-first, property-driven approach becomes essential to prevent hidden bugs and ensure design correctness.

Summary: A Long-Awaited Shift in Hardware Design

For the first time, the industry can realistically move toward a workflow where design intent is explicit, properties are complete, and RTL correctness is provable from day one. Advances in modeling, property generation, formal verification, and AI have finally aligned to make assertion-first hardware design achievable.

LUBIS EDA is helping open the door to this future—one where hardware design begins not with RTL, but with formal, executable intent.